FIG. 9 shows an example of a conventional vertical insulated-gate semiconductor device having a trench structure. The semiconductor device 9A shown in the figure includes a first n-type semiconductor layer 911, a second n-type semiconductor layer 912, a p-type semiconductor layer 913, an n-type semiconductor region 914, a trench 93, a gate electrode 94 and a gate insulating layer 95.
The first n-type semiconductor layer 911 serves as a base of the semiconductor device 9A. The second n-type semiconductor layer 912, the p-type semiconductor layer 913, and the n-type semiconductor region 914 are stacked on the first n-type semiconductor layer 911.
The trench 93 is formed so as to penetrate through the p-type semiconductor layer 913 and the n-type semiconductor region 914 to reach the second n-type semiconductor layer 912. Inside the trench 93, the gate electrode 94 and the gate insulating layer 95 are provided. The gate insulating layer 95 insulates the gate electrode 94 from the second n-type semiconductor layer 912, the p-type semiconductor layer 913 and the n-type semiconductor region 914. The gate insulating layer 95 is formed along the inner surface of the trench 93.
The p-type semiconductor layer 913 includes a channel region. The channel region is along the trench 93 and in contact with the second n-type semiconductor layer 912 and the n-type semiconductor region 914.
Regarding the semiconductor device 9A thus configured, it is preferable that the on-resistance is low from the viewpoint of reducing energy loss. To prevent dielectric breakdown, it is preferable that the dielectric withstand voltage is high. Also, there is a demand for a reduced threshold voltage so that the semiconductor device can be driven by applying a relatively low voltage to the gate electrode (see Patent Document 1, for example).    Patent Document 1: JP-A-2006-32420